FIG. 1 illustrates a prior art assembly 100 including an integrated circuit 102 (illustrated as a “flip chip”) adapted for physical and electrical attachment to a earner substrate 110 by way of a plurality of solder interconnects 106. While the integrated circuit 102 and the carrier substrate 110 are shown to be separated in FIG. 1, the interconnects 106 are adapted for providing connectivity between bond pads 104 of the integrated circuit 102 and copper landing pads 112 of the carrier substrate 110, when assembled.
To improve connectivity with respect to the copper landing pads 112 of the carrier substrate 110, various prior art systems include lead-tin (Ph/Sn) “pre-solder” material 108 that is printed within solder wells 114 of the carrier substrate 110 over the corresponding copper landing pads 112, in the manner shown. Thus, during assembly, the interconnects 106 and such solder material 108 may be subjected to a high temperature reflow process that facilitates a connection between the interconnects 106 and the solder material 108 and underlying landing pad 112. With assemblies being manufactured with smaller and smaller geometries (and thus smaller landing pads 112, wells 114, etc.), however, it has become increasingly difficult to fill such smaller wells 114 with the printed solder material 108, etc.
FIG. 2 illustrates another prior art assembly 200 again including an integrated circuit 202 and a carrier substrate 210, where interconnects 206 are adapted for providing improved connectivity between bond pads 204 of the integrated circuit 202 and copper landing pads 212 of the carrier substrate 210, when assembled. Unlike the prior art assembly 100 of FIG. 1, the assembly 200 substitutes the solder material 108 with a plated copper material 208 and an underlying copper seed layer 214 to facilitate conductivity. By using such plating technique (instead of the aforementioned printing technique), the copper material 208 is capable of better accommodating tighter geometries. Still yet, an immersion tin layer 216 is employed to prevent a surface of the plated copper material 208 from oxidizing, etc.
Thus, such plated copper material 208 and copper seed layer 214 provides enhanced electrical and mechanical connectivity between the interconnects 206 and the underlying landing pad 212, particularly for flip chip assemblies with smaller geometries. However, such plated copper material 208 significantly adds to the expense and thus a cost of the resultant assembly 200.
There is thus a need for addressing these and/or other issues associated with the prior art.